The present invention relates to systems for writing data into a flash-memory storage device in a way that optimizes the speed of reading data without sacrificing storage space.
Flash-memory storage devices are well-known in the art of computer engineering. Simple flash-memory cells typically contain one bit of data per cell, and are referred to in the art as SLCs (single-level cells). One of the main goals in developing flash-memory storage devices is to increase storage density in order to reduce the amount of silicon used, thereby reducing the cost of the device.
A well-known method for increasing the storage density in flash-memory storage devices is to implement what is referred to as MLCs (multi-level cells), which are based on establishing and utilizing three threshold voltage-levels, rather than one threshold voltage-level in each cell. MLC technology is described in an article published by Datalight Inc., Bothel, Wash. entitled “Technology Comparison—SLC and MLC Flash” (available at www.datalight.com), as well as taught by Tanaka, U.S. Pat. No. 6,643,188 (hereinafter referred to as Tanaka '188), hereby incorporated by reference as if fully set forth herein.
While doubling the storage capacity of the device, MLC technology requires more time to read the memory. One possible reason for the longer reading time is that the reading operation may require two voltage comparisons rather than one. The prior art teaches methods for writing at relatively fast (and slow) speeds to pages in MLC storage devices, but the prior art does not teach any methods for reading data from MLC devices at the high speeds that are typical for SLC storage devices.
The prior art teaches methods for overcoming the speed limitation of MLC storage devices by sacrificing the “slow pages” and using only the “fast pages” (defined below in the Summary). A prior-art example of such a method is disclosed by Lasser et al., US Patent Application No. 20060155919 (hereinafter referred to as Lasser '919), assigned to the assignee of the present invention, and hereby incorporated by reference as if fully set forth herein. This improvement in speed is provided at the expense of a significant loss of storage space. In such devices, the slower part of the storage area is not used at all, reducing the original storage capacity of the device.
It would be desirable to have a variable read-speed storage device in which part of the MLC data can be read much faster than other parts of the data, without wasting a significant part of the storage area by leaving the slower part unused.